Addressing Clock Tree Synthesis Challenges

Debaprasad Daxiniray & Chinmaya Masali (Sankalp Semiconductor)

Abstract:

Clock tree synthesis (CTS) plays an important role in building well-balanced clock tree, fixing timing violations and reducing the extra unnecessary pessimism in the design. The goal during building a clock tree is to reduce the skew, maintain symmetrical clock tree structure and to cover all the registers in the design. We have captured some problematic scenarios and the problem solving approaches in this article.

Clock tree network enables in making design clean from a timing perspective. However, it is responsible for more than one third of the total power consumption of the chip. The impact of variations in the clock path is more than 2 times the other paths in the design. These variations in-turn affects the timing paths. Let us take an example; Due to the variation, if the clock path to the launching register is slowed down by 100ps and the clock path to the capturing register is fastened by 100ps then it impacts the setup constraint by adding 200ps more to it, this in-turn affects the timing path by making it more critical. Here we can see the importance of building a balanced clock tree. We will discuss on the timing improvements and methods to reduce the variations in the clock tree. The steps followed in building a customized clock tree and the steps followed to bring down the variations in the clock tree has been depicted in the following sections.

1. Addressing design challenge of registers placed far apart

The section describes the problem encountered and fixes while building the clock tree when registers are far apart. Referring to the diagram (Figure-1) below the clock port is positioned at the middle of the bottom part of the chip. The encircled part at the bottom of the chip represents the digital glue logic that is communicating with the digital logic (beside analog block) at the top of chip. There are large magnitude of setup violations observed on these paths. Being a full chip design, the output delay was critically constrained that led to large timing violations on the output pads. Here are some methods targeted to meet setup timing by building a customized clock tree.

Automatic clock Tree Synthesis Technique

With Automatic clock tree synthesis, the CTS engine puts a lot of buffers across the chip that are not desired. The registers near the clock port face large insertion delays. This effect is due to the clock balancing nature of automated CTS engine. The Clock tree structure will be H-tree similar to the figure-1. Since the chip size is large, the number of buffers are huge on the clock tree due to clock balancing. This renders the experiment not to be useful.

 

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