Our teams have rich memory platform expertise including experience in a comprehensive set of memory compilers utilizing foundry bitcells such as:

  •  Performance optimized low VDD capable memories with multi periphery VT options
  • Ultra high performance L1 Fast Cache Instances (FCI), Single & Dual Port RAM Compilers
  • Flexible periphery options
  • High performance
  • Low leakage

Our experts are experienced in a large selection of standard, low power and yield optimization features, comprehensive Testing & Diagnosis Systems and Self-Test & Repair Solutions

Core Design Expertise

  • PPA Analysis
  • Bit Cell Analysis
  • Memory Margining
  • Sense Amp Offset Analysis
  • Race-ratio analysis
  • CCS noise char simulations
  • Timing power
  • Input cap (calculations)
  • Power characterization
  • Leakage builder analysis
  • Logical vs netlist (ESPCV)
  • Circuit Check
  • Bitmap view verification
  • Front End view verification
  • Data accuracy of .lib
  • Trend Check analysis for .lib
  • Simulator Settings Analysis
  • Flat vs. Stitched Net-list comparison

Memory Development



Touchstone is a characterization solution that provides timing and power parameters. The solution performs characterization at Instance (cell to lib) and compiler level and can be seamlessly integrated into any custom environment. The method of specification of characterization vectors is based on high level operations, e.g. read, write, etc. Tightly coupled with MC2, Touchstone provides options to present trends of calculated parameters.